Electronic systems and circuits have made a significant contribution towards the advancement of modern society and are utilized in a number of applications to achieve advantageous results. Digital computers, calculators, audio devices, video equipment, telephone systems and a number of other electronic systems and circuits have facilitated increased productivity and reduced costs in a number of activities, including the analysis and communication of data, ideas and trends in most areas of business, science, education and entertainment. These electronic systems usually include a variety of components that communicate with each other in the performance of their prescribed tasks.
The speed and efficiency of communications between components of an electronic system are factors that can significantly impact performance of the system. For example, a number of different electronic systems incorporate components that rely on microprocessors to perform arithmetic operations, manipulate data, make decisions, and issue control commands related to the operations of the system. Virtually all microprocessor systems rely on a main memory to store instructions and information related to applications associated with the system or circuit. Efficient communication of information to and from the main memory impacts the ability of the microprocessor and other components in an electronic system or circuit to perform prescribed functions. There are numerous examples of electronic systems or circuits comprising components that depend upon efficient communications with a main memory component in order to operate properly.
FIG. 1 shows a schematic of one embodiment of a prior art computer system 100, one example of an electronic system that is impacted by constraints in the transfer of communications between it components. Computer graphics system 100 comprises a central processing unit (CPU) 101, a volatile main memory 102, graphics controller 103, non-volatile read only memory (ROM) 104, mass storage device 105, a signal input/output communication controller 106, keyboard 108, printer 109 and display monitor 110, all of which are coupled to bus 107. CPU 101 handles most of the control and data processing. Main memory 102 provides a convenient method of storing data for quick retrieval by CPU 101. Graphics controller 103 processes image data in pipelined stages. Non-volatile ROM 104 stores static information and instructions for CPU 101. Mass storage device 105 stores information associated with multiple images and applications. Signal input/output communication controller 106 controls external communications ports (not shown). Keyboard 108 operates as an input device. Printer 109 prints hard copies of graphical images and display monitor 110 displays graphical images. Bus 107 acts as a communication medium between the components.
Most electronic systems have certain access constraints that impact communications between devices in an electronic system. Transferring information to and from a device is usually governed by requirements based upon a combination of items such as the format of a media and/or allocation methods used by an operating system, etc. For example, main memory and bus protocols typically set alignment requirements a component (such as a direct memory access (DMA) engine or controller in the processor) that orchestrates transfers must contend with. Main memory and buses also usually dictate the minimum byte granularity or number of bytes that are transferred in each memory access and bus each cycle. In addition, a DMA is typically required to expend a certain minimum time establishing access with a main memory or a communication bus. These requirements often result in inefficiencies and delays in transferring information when a piece of data is not a size that is a multiple of the minimum granularity and not aligned to a natural boundary memory address that is a multiple of the minimum granularity. Typically these inefficiencies and delays adversely affect the performance of the electronic system or circuit.
The alignment of addresses in both the sending and receiving devices significantly affects data communications. Moving data between addresses (e.g. between a main memory and another device) that are aligned to an integer multiple of the same power of 2 as the maximum transfer size (e.g. 2048) is relatively straightforward. For example, these transfers are very efficient in systems with 32 byte transfer bursts because they consist of convenient data sizes (e.g. 2048) sent to nicely aligned addresses (e.g., some binary starting address with A[4:0] all set to zero). Moving the data to another memory address (e.g. in a main memory) that is not aligned to an integer multiple of the same power of 2 as the maximum transfer size (e.g. 32 bytes) is more difficult and typically results in communication delays. In addition, data transferred to and from mismatched positions in between natural address boundaries of a main memory and peripheral devices also increase communication delays.
In one example of an electronic system, data is bus mastered from a mass storage device into main memory, including all of the header information, and the payload data is transmitted from main memory to another device. A mass storage device usually comprises many types of data and is organized in sectors. For example, a digital video disk (DVD) usually includes audio, on-screen display (OSD), navigation packets and video data. A system including a DVD is typically required to move variable length data to any starting address in main memory. After the information has been bus mastered into a main memory a processor or controller then interrogates the header information to determine the type of data, the starting address, and the length of data in each of the sectors read from a mass storage memory (e.g., DVD). The processor or controller then moves the data payload to its destination. For example, audio data may be sent to a hardware device that assists in the decoding of the audio data and video data may be sent to a MPEG 2 video decoder. However, headers from the mass storage device are often non binary lengths and not usually transferred to the other devices. This leaves payload sizes that are nonbinary in length and less than a desirable multiple of the power of 2, making them an in convenient size for transmission.
Additional inefficiencies typically occur when a component that orchestrates accesses (e.g. a DMA engine or processor) to a main memory limits accesses t o certain types of communication transfers. A data payload may be a byte count length the hardware does not support and therefore increases the difficulty in moving the data around in memory. In some electronic systems that include a synchronous dynamic random access memory (SDRAM) hardware limits access to specific types because of constraints inherent in SDRAMs and limitations of the SDRAM controller in a host processor. In these systems, accesses are usually limited to types such as a byte (8 bit), word (16 bit), double word (32 bit), long word (64 bit) or 32 byte burst (typically four 64 bit values in a single burst). By limiting accesses to certain types of communications transfers, other types of transfers are not supported efficiently. For example, a typical SDRAM system does not directly support 3 byte, 5 byte, 6 byte, 7 byte, and 9-31 byte transfers efficiently.
Communication inefficiencies can become further exacerbated in electronic systems that rely on information being transmitted in bursts of a specific length. Each transfer to or from a main memory typically has a relatively large overhead and not transferring the full capacity of a burst is very inefficient. For example, in a typical SDRAM system a 32 byte burst transfer full of relevant data uses the approximately the same amount of overhead as a 32 byte burst transfer comprising a single byte or relevant information except with the full 32 byte burst transfer a lot more information is conveyed in the payload. Smaller amounts of information communicated in each payload results in less efficient utilization of communication bandwidth.
Inefficient communication of information to and from devices usually has a substantial impact on the ability of an electronic system or circuit to perform its prescribed functions . Communication delays or inefficiencies are particularly detrimental in electronic systems or circuits that require data to "stream" smoothly. For example, most electronic systems or circuits that include a DVD have strenuous data movement requirements so that the different types of data such as audio and video flow in a sufficient stream to be perceived by human sense as continuous. If the data does not sufficiently flow in most electronic systems with DVD the systems will not operate properly and will not provide adequate results.
What is required is a system and method for conveniently and efficiently conveying information, including data that does not line up on a natural memory boundary or has mismatched byte alignments between a source and destination. The electronic system and method should be able to expediently communicate information and facilitate smooth streaming of data. The electronic system and method should ensure the information is properly aligned when the transfer is complete, including handling data alignment down to a byte boundary both at a source and a destination. The electronic system and method should minimize impacts due to access constraints of a media format or operating system memory allocation method and efficiently communicate data that is not a length directly supported by an electronic system's hardware. The electronic system should maximize utilization of available capacity in intermediate communication bursts between a first and last burst of a transfer and minimize the number of non optimal memory accesses.